1. Technical Field
The present invention relates generally to integrated circuits. More particularly, the present invention relates to clock networks in integrated circuits.
2. Description of the Background Art
A programmable clock network in an integrated circuit may be configured to link various transceiver channels with different clock sources. As such, the clock network may determine multiple channel/clock configurations for the interface. In addition, the performance of the clock network is a substantial determinant of transceiver performance in terms of jitter, skew, latency, and other measures.
On one hand, a high performing and flexible clock network may increase the usability of the interface and so reduce non-recurring engineering needed to satisfy customer requirements. On the other hand, the implementation of a clock network that is both flexible and high-performance is generally expensive in terms of die area used and power consumed.
It is highly desirable to improve the design of clock networks for integrated circuit interfaces with multiple transceiver channels.